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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY g_inv IS
	PORT (	in0				: IN  STD_LOGIC;
      		q	 			: OUT STD_LOGIC
			);
END g_inv;

ARCHITECTURE behav OF g_inv IS
BEGIN
	q <= NOT in0;
END behav;